Comments (10)
Please refer to the riscv_rand_instr_test
https://github.com/google/riscv-dv/blob/master/yaml/testlist.yaml#L76
You can increase the ratio of loop instructions to generate more backward branch instructions.
The loop instruction is generated by below class, you can enhance it if you want to cover other backward branch scenarios.
https://github.com/google/riscv-dv/blob/master/src/riscv_loop_instr.sv
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Just increase the number 4 (this is the knob for the possibilities)
+directed_instr_1=riscv_loop_instr,4
You can also remove the other directed tests from the command line options if you don't want to include them in your test.
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BTW, are you using it for swerv core? I have done some work locally, the ISS/RTL sim comparison part as the tracer from swerv core doesn't have the rd value information. Let me know if you need help on this.
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I mean the external trace interface doesn't provide the result of the instruction. Maybe there'e some other way to get the complete trace info?
https://github.com/westerndigitalcorporation/swerv_eh1/blob/master/design/swerv.sv#L34
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Sure, let me close this issue for now, we can discuss with a separate thread.
I actually have a plan to open-source an integrated TB with swerv-eh1. Adding whisper(ISS) should be straightforward, but I failed to install in my local (got core dump). If you get it work, it will be great to add this support in the riscv-dv repository. Let me if you question with ISS integration.
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