How long it takes to synthetize the Toolchain in Arty 35T ? about learn-fpga

[mithro]

BTW Yosys + nextpnr-xilinx is currently unmaintained. It will eventually hopefully replaced with the nextpnr interchange format work in the future (which will be used for all of the Lattice, Xilinx and QuickLogic flows).

[mithro]

You might want to try examples @ http://symbiflow-examples.rtfd.io/ for yourself. The currently developed Arty 35T based on Yosys + VPR is quite a bit slower than the ECP5 / iCE40 toolchain based on Yosys + nextpnr but it is getting better.

BTW There are plenty of easy ways to help improve the performance if you are a Python / C++ developer.

[BrunoLevy]

@mithro yes, I have seen it (and I have updated the symbiflow installation script based on the latest version).

@benitoss: the blink examples takes a few seconds to generate (there is not much difference between symbiflow and yosys/nextpnr-xilinx for such a small design).

Some stats for larger designs:

For a small core (femtorv32-quark RV32I, 1.2K LUTs, 400 FFs),

• symbiflow takes 2min13s
• yosys/nextpnr-xilinx takes 25s

For a larger core (femtorv32-petitbateau RV32IMFC, 5K LUTs, 1K FFs)

• symbiflow takes 5 min 34s
• yosys/nextpnr-xilinx takes 1 min

But symbiflow quickly evolves, so it is a good idea to support both for now (and it is an even better idea - I think that @mithro won't disagree - to contribute to make symbiflow better/faster !!!).

[benitoss]

Thanks @mithro and @BrunoLevy for the answers.
They are acceptable times for the yosys/nextpnr-xilinx option.
I will try first with my board and later maybe I try to implement in ICeStudio + Apio

Thanks again.
I close this issue