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16-x-16-bidirectional-memory

16 x 16 Bidirectional Memory

16-x-16-synchronous-memory

16 x 16 Synchronous Memory

16_4-priority-encoder

16_4 Priority Encoder

32x8-asynchronous-rom

32x8 asynchronous ROM. Read_address and ouput_en are two inputs of ROM. Used $fmonitor to store the location(@location_in_hex) and content(conten_in_hex) that is read in mem.txt file and used $readmemh system task to: a. Initialize ROM from data stored in “memory1.txt” file. Each location stores the content equivalent to its read_ address (i.e. 5 is stored in 5th location of ROM). Used self testing test bench to verify that the content and the read_address are equal to each other for a particular location. b. Initialized ROM from data stored in “memory2.txt” file. Stored the data in address ranging from 15 to 28. Verified the content stored using test bench.

4x4-sequential-multiplier-using-booths-algorithm

Designed 4x4 sequential multiplier using booths algorithm

8-bit-arithmetic-logical-unit

8-bit Arithmetic Logical Unit

8-x-3-priority-encoder

8 x 3 Priority Encoder using concurrent statements

8_3-priority-encoder-using-dataflow-modeling

8_3 priority encoder using dataflow modeling

adb-data-conversion

ADS-B Exchange daily flight data json conversion and processing using R. Automated shell script to fetch data for set duration and execute R script.

artificial_intelligence_based_new_eleusis_game_solver

New Eleusis Game Solver

asynchronous-ram-cy6264

Design and verify the functionality of the Asynchronous RAM CY6264

design-and-verification-of-functionality-using-core-generator

Using Core generator Designed and Verified functionality of following blocks i. 5x5 unsigned multiplier ii. 32x4 Simple Dual Port Ram iii. 5 Bit Adder/Subtractor Circuit using Fabric(Verify using FPGA Editor) iv. 3 Bit Adder/Subtractor Circuit using DSP48(Verify using FPGA Editor) v. 8x8 ROM with initial value provided from .coe file

dff-with-asynchronous-preset-and-reset-and-verified-for-xilinx-virtex-6-fpga

DFF with asynchronous preset and reset and verified for Xilinx Virtex 6 FPGA

digital-circuit-design

Digital circuit design. After synthesis is over, modified the code so that buffer (BUF) provides a delay of 5 units, AND gate of 4 units and OR gate of 3 units. D Flip Flop has set up requirement of 3 units and hold requirement of 4 units. Used specify block for defining setup and hold requirements. Calculated the minimum time period (or maximum frequency). Provided clock input with smaller time period than required to observe setup and hold violations. Verified proper functionality of the circuit after this increase in the time period to the required value.

first-contributions

🚀✨ Help beginners to contribute to open source projects

frequency-divide-by-8-circuit-using-t-flip-flop

Frequency divide by 8 circuit using T Flip Flop

gaspred

Gas Price Prediction Service

gopigo3

The GoPiGo3 is a Raspberry Pi Robot!

graduation

$ git remote <graduation> yearbook

johnson-counter--6-bits-

Johnson Counter 6-bits

knn-based-mnist-digit-recognition

Custom kNN based MNIST digit recognition. No built in kNN function used to process data.

network-manager

Network Manager

priority-arbiter

Priority resolver receives four requests req_a, req_a, req_c, req_d and generates four grants gnt_a, gnt_b, gnt_c, gnt_d. At initial stage A has higher priority over B, B has higher priority over C and D has the least priority. At the later stages, resolver uses Least Recently Used Algorithm for generating grants based on requests received. On transcript display the devices that are generating request and the device that is provided grant

probability_solver

Implemented a program that computes and returns the probability of any conjunction of events given any other conjunction of events for 5 argument Bayesian network.

puzzle_path_finder

A program to read in and solve path finding puzzles using A* search algorithm. Each puzzle consists of a sequence of integers. At each step in the puzzle, we move exactly the number squares indicated by integer in the square you are in.

py_genome_next_generation_sequencing

ring-counter--6-bits-

Ring Counter 6-bits

robot_mazesolver

Win It

rom-design

ROM Design

sequence-detector-using-gate-level-modeling

Sequence detector using Gate Level modeling