Comments (4)
duplicate of https://repost.aws/questions/QUPA0GiM6GTBiVzj45Aj0IQg/ddr-performance-drop-with-specific-address-access-pattern
from aws-fpga.
Thanks Chakra for the reply.
I guess you might have tagged the wrong repost link.
https://repost.aws/questions/QUPA0GiM6GTBiVzj45Aj0IQg/ddr-performance-drop-with-specific-address-access-pattern
In our case the address access pattern is random and access lengths are short (64B or 128B)
I assume these are not user configurable at this point to take performance advantage for the access patterns listed above.
"ROW_COLUMN_BANK_INTLV" addressing mode and
"Force Read and Write commands to use AutoPrecharge"
from aws-fpga.
Thank you for the pointer, somehow I copied wrong link from re:post.
Correct, our DDR controllers are not user configurable so random access patterns shall result in poor performance.
from aws-fpga.
Thanks for confirming !!
from aws-fpga.
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