Comments (3)
David-Garcia-Polo
commented on June 8, 2024
Is there any traction with the issue? will it be possible to open source the SVDConv code so I fix it myself?
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David-Garcia-Polo
commented on June 8, 2024
Seems to be fixed in latest SVDConv uploaded here, but why have the new macros __IOM, __IM and __OM been introduced? Our customers will need to update the core_cmx files to be able to use the header files produced with that SVDConv. some of our customers are very reluctant to change any file, so it will force us to mantain two versions of the header files.
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David-Garcia-Polo
commented on June 8, 2024
solved in v3_2_48
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Related Issues (20)
- Main Cortex-M55/M85 EWIC registers not present HOT 4
- Possible bugs in `__STREXW` and `__LDREXW` in cmsis_armcc.h and cmsis_armclang.h HOT 5
- SVD multiple enumeratedValues occurrences meaning HOT 2
- Filter State variable access with Python Wrapper for arm_biquad_casd_df1_inst_f32 HOT 1
- Issues with new ARMv8 MPU attributes HOT 1
- Issue with osDelay in TC_osKernelResume_1 HOT 2
- RTX4 EXCLUSIVE_ACCESS macro undefined for GCC compiler HOT 2
- Versioning of CMSIS Core missmatch HOT 3
- Add HOST support HOT 2
- Output Mismatch in ARM mult , scale, Complex real mult in CMSIS 5.9 version HOT 1
- `CMSIS_DEPRECATED` for Cortex M? HOT 1
- Error in the description of CMSIS-SVD HOT 1
- The number of `enumeratedValue` elements in the `enumeratedValues` element if the `derivedFrom` attribute is present HOT 6
- EMAC_iMXRT1064.c file is not compatible with fsl_enet driver in Keil HOT 3
- [SVDConv] `writeConstraint` in `register` crashes SVDConv HOT 2
- How to build a library in the Ti env. HOT 1
- Thread switch on osKernelRestoreLock? HOT 2
- RTOS2 - memory block pools vs byte pools? HOT 7
- armv8-m register define doesn't include BPU HOT 2
- Extension of osKernelGetTickCount() to provide monotonic tick counter is in error. HOT 3
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