Name: Syed Arham Hashmi
Type: User
Company: Micro Electronic Research Lab
Bio: Computer System Engineering Student | Research Trainee @ MERL | RICS-V | Verilog | System Verilog | Python
Location: Karachi,Pakistan
Syed Arham Hashmi's Projects
Apartment Management System is a Desktop Application developed using Python/Tkinter and mysql database.
Ariane is a 6-stage RISC-V CPU RV64-GC
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
"Bank Management System: This repository contains a C++ implementation for managing bank operations, including account management, transactions, and user authentication."
This repository is the contain systemverilog version of Buraq-mini with a seperate branch for veriloator team.
This repository contain the implementation of CPU scheduling algorithm FCFS , SJF , PRIORITY , ROUND ROBIN in python
This repository contains an extensive learning journey of FPGA
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
The OpenPiton Platform
Linux Kernel for OpenPiton
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog
This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".
This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language