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antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

berkeley-hardfloat

cgra-flow

CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.

cgra-mapper

An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.

circt

Circuit IR Compilers and Tools

circt-hls

CIRCT-based HLS compilation flows, debugging, and cosimulation tools.

computer-science

:mortar_board: Path to a free self-taught education in Computer Science!

dsx_kcxg

个人资料，合肥工业大学宣城校区2019年-2020年第二学期（大三下学期），与物联网工程专业的课程有关资料，含课件、实验报告、课设报告等

dynamatic

figure_

Some ducuments Photos

fir_filter

In signal processing, a finite impulse response (FIR) filter is a filter whose impulseresponse(or response to any finite length input) is of finite duration, because it settles to zero in finite time. This is in contrast to infinite impulse response (IIR) filters, which have internal feedback and may continue to respond indefinitely (usually decaying).

gemmini

Berkeley's Spatial Array Generator

github_scalesim

hector

A hardware synthesis framework with multi-level paradigm

hector_template

heterocl

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

ir_dot

A “Toy” Script transoforms MLIR Affine Dialect to Dot Visualized Format

iree

A retargetable MLIR-based machine learning compiler and runtime toolkit.

llvm-cfg-dfg-pass

Simple passes for CFG and DFG analysis

llvm-project-mine

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

mlir-aie

An MLIR-based toolchain for Xilinx Versal AIEngine-based devices.

mlir-cgra

An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.

mlir-hello

MLIR Sample dialect

mlir-pass-tour

（目前mlir的standalone只有如何添加dialect的模版，官方代码中TODO: Register standalone passes here.）和Polygeist的代码，实现了一个简单的Pass，功能是给scf.for添加一个自定义的attribute，并很粗糙地实现了一个opt-like工具

mlir-tutorial

modern-cmake-for-cpp

Modern CMake for C++, published by Packt

morpher

An Open-Source Tool for CGRA Accelerators

mqsim

MQSim is a fast and accurate simulator modeling the performance of modern multi-queue (MQ) SSDs as well as traditional SATA based SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and the full end-to-end latency of requests in modern SSDs. It is described in detail in the FAST 2018 paper by Arash Tavakkol et al., "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices" (https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18.pdf)