Comments (1)
Interesting. This is a bug in the register offset descriptions in archinfo, which are not consulted during the lifting process since that happens purely in libvex.
It looks like this was originally the fault of a bug in the script to autogenerate those offsets. I will fix it shortly.
from archinfo.
Related Issues (20)
- AMD64 RIP is marked general purpose but x86 EIP is not HOT 5
- `archinfo.arch_arm.is_arm_arch` returns `False` for AArch64 HOT 5
- Import issue HOT 1
- How to install archinfo==9.2.19.dev0 HOT 3
- Implement a plugin system to allow arches to be added or registered by other projects HOT 1
- Remove os-specific information HOT 2
- Refactor arches to be singletons
- Synchronize segment register names for i386 and amd64 HOT 1
- How to fix this error: archinfo.arch | Please look up and add dynamic tag type 0x70000001 for AMD64 HOT 2
- instruction_endness not set for ArchARM & ArchAArch64 HOT 8
- LICENSE missing on pypi HOT 1
- New Register class - Weird ARM32-Name HOT 8
- KeyError: 'ip' during import HOT 5
- import error on archinfo 8.18.10.25 HOT 6
- MIPS64 and branch_delay_slots HOT 4
- Confusing error message when pyvex fails to import HOT 5
- Adding archinfo to CI HOT 2
- A common thumb mode prolog ignored HOT 3
- architecture HOT 1
- Vanilla `archinfo` seems to have dependencies problem HOT 1
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from archinfo.