amungo / nut2nt Goto Github PK

I would like to know if someone was able to develop a GPS receiver within the Lattice FPGA of this board. I have attempted to create a design based on this thesis, but I don't think I can grasp the details hidden within the blocks described in Figure 3.5. My main issue is in acquiring the GPS signal as it changes phase by 180 degrees for both the C/A code and data bit transitions.

design.zip

I think I need to find out which Integrate and Dump outputs are used for which stage in tracking the signal, detailing how long the integrate and dumps need to run exactly, and keeping track of these phase changes. I have a different but similar idea to this design, separating the two stages of carrier locking and code locking. The carrier locking stage would acquire a lock on the frequency and phase, but wouldn't care if the lock is on the actually carrier frequency or its inverse. Every time the carrier switches between its phase and inverse phase, a flag is sent. This would advance the code generator instead of a separate code DCO.