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6502_65c02_functional_tests

Tests for all valid opcodes of the 6502 and 65C02 processor

aholme-6502

Andrew Holme's Verilog 6502

axi4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

bbcmicro_mister

BBC Micro B and Master 128K for MiSTer

beebfpga_mister

bomdbase

documentation

OSVVM Documentation

dpram

DpRam

hagl

Hardware Agnostic Graphics Library for embedded

jarv

Just Another RISC-V

lattice-vhdl

make-fpga

mega65-core

MEGA65 FPGA core

mos6502

A fast & simple MOS 6502 CPU emulator written in C++

mos6502-trace

Traces execution of specified binary using mos6502 emulator by Gianluca Ghettini

multisim-mk

Support for makefile driven VHDL simulation projects

notepad-plus-plus

Notepad++ official repository

nvc

VHDL compiler and simulator

osvvm

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

osvvm-common

Packages that implement OSVVM's model independent transactions and other shared verification component support packages. Required for all OSVVM verification components. AddressBusTransactionPkg - AXI, AxiLite, ... StreamTransactionPkg - AxiStream, UART, ...

osvvm-scripts

OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation

osvvmlibraries

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

pyvcd2gtkw

Generates GTKWave save files from simulation VCD files

quartus-mk

makefile support for Quartus designs

t65

T65(b) 65xx compatible core. In an effort to merge and maintain bug fixes

tinyprintf

A tiny printf and sprintf library for small embedded systems

tyto2

The Tyto Project - version 2

tyto_project

The Tyto Project

uart

OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verification component with error handling for parity, stop, and break errors.

uvvm

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/