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arduino

open-source electronics prototyping platform

ariane

Ariane is a 6-stage RISC-V CPU

awesome-courses

:books: List of awesome university courses for learning Computer Science!

brookgpu

The original Stanford Code befor becomming Brook Plus - pulled from Subversion 1889

cache

Verilog Cache-4Ways IP development

cntk

Microsoft Cognitive Toolkit (CNTK), an open source deep-learning toolkit

convnetasic

cores-swerv

SweRV EH1 core

cs3220_gpu

darknet

Convolutional Neural Networks

dramsim2

DRAMSim2: A cycle accurate DRAM simulator

e200_opensource

The Ultra-Low Power RISC Core

etna_viv

laanwj's personal etna_viv fork -- upstream repository is https://github.com/etnaviv/etna_viv

floatpointarithmetic

Float Point Add, Multiply and Division.

gplgpu

GPL v3 2D/3D graphics engine in verilog

gveri

GVeri - A Verilog HDL editor under linux

integerarithmetic

Integer arithmetic: 32-bit adder, subtraction, multiplication, division.

interconnector

Memory access interconnector which handles the priority and bandwidth

lizard

Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL

mac

Memory Access Controller handles the actual bank, row, col sram request

malc

MIPS Assemble Language Compiler

mcgsim

Linux version of the simulation where it provide the MS solution in http://cs.lth.se/eda075/lectures/

minerva

A 32-bit RISC-V soft processor

mipscpu

A six pipelined (Fetch, Decode, Issue, Execute, Memory, WriteBack) cpu that only implements parts of mips instructions in Verilog

mipscpu2

The second generation of MIPS CPU with pipelined design

mipssimulator

Mips CPU binary code simulator with C++ code in cycle model

modelfactory

A Matlab/Octave toolbox to create human body models

ncsu-low-power-rfid

Verilog code for a low power RFID chip that will communicate with I2C sensors.

opencnn

Open Convolution Core

openprojects