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asplos24-micro-update-lifting

Companion artifact for ASPLOS '24: Lifting Micro-Update Models from RTL

autoslides

axiomatic-operational-examples

Experimental examples for axiomatic-operational

axiomatix

c3-simulator

C3-Simulator is a Simics-based functional simulator for the X86 C3 processor, including library and kernel support for pointer and data encryption, stack unwinding support for C++ exception handling, debugger enabling, and scripting for running tests.

daikon

Dynamic detection of likely invariants

db-project

Parallel join optimisation scheme for PostgreSQL

deterministic_model

Deterministic_Models

helloworld

Getting Started

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

llvmlite-dataflow

Generate dataflow graphs with the llvmlite Python library

multi_vscale

Verilog version of Z-scale (deprecated)

ps2sc

Bounded model checker for PS 2.0

pyclid

Python wrapper for UCLID5

pyeda

Python EDA

pyvcd

Python package for writing Value Change Dump (VCD) files.

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

riscv-sodor

educational microarchitectures for risc-v isa

sdram-controller

Verilog SDRAM memory controller

syncuit

circuit problem synthesis

tomasulo-machine

uclid

UCLID5: formal modeling, verification, and synthesis of computational systems

vossii

The source code to the Voss II Hardware Verification Suite

zipcpu

A small, light weight, RISC CPU soft core

zsim

A fast and scalable x86-64 multicore simulator