3i-hust-fpga Goto Github PK
Type: Organization
Type: Organization
Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
FPGA Implementation of the proposed model in master thesis.
Machine learning in FPGAs using HLS
The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))
Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation.
Neural network visualizer
PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
Implement Tiny YOLO v3 on ZYNQ
[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
A declarative, efficient, and flexible JavaScript library for building user interfaces.
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Open source projects and samples from Microsoft.
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Data-Driven Documents codes.
China tencent open source team.