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10xcelerator

ahb3lite_memory

Multi-Technology RAM with AHB3Lite interface

ahblitepart2

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

arty_a7_demo

Demo of burning a simple adder code on ARTY_A7 (FPGA) using Vivado.

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

clang-builtin-tutorial

cloud-v-ci-hifive-unleashed

This repository triggers the job build which runs on hifive unleashed

cloud-v-git-automation

Odoo module for integration of Cloud-V GitHub app with user repositories

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

corev-llvm-project

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6-1

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6-pulp

This is the fork of CVA6 intended for PULP development.

cva6_linux_boot

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

cvw-arch-functional-verif

cvw-arch-verif

The purpose of the repo is to support CORE-V Wally architectural verification

force-riscv

Instruction Set Generator initially contributed by Futurewei

fwrisc

Featherweight RISC-V implementation

ibex-core-verification-environment

infinite-isp

A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.

infinite-isp_firmware

Infinite-ISP Image Signal Processing Pipeline Firmware for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit (coming soon).

infinite-isp_fpgabinaries

Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit.

infinite-isp_referencemodel

A Python based fixed-point implementation of the Infinite-ISP design for ASIC and FPGA design and verification.

infinite-isp_tuningtool

Infinite-ISP Tuning Tool is a console-based ISP (image signal processor) tuning application that is specifically designed to tune various modules in the Infinite-ISP_GM.

jenkins-ci

For testing github webhook with jenkins jobs

llama.cpp

Port of Facebook's LLaMA model in C/C++