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3d-marker-generator

This code generates a board of fiducial markers from different views

aes-studies

AES in Hardware: N-Studies

aoc22

aow

Algorithm of the week

asip-dsl

A domain-specific language for making ASIPs that will be converted into VHDL code for subsequently running them on FPGAs

expose

A Dynamic Symbolic Execution (DSE) engine for JavaScript. ExpoSE is highly scalable, compatible with recent JavaScript standards, and supports symbolic modelling of strings and regular expressions.

fiver

fpga-i2c-minion

A simple I2C minion in VHDL

fpga-union-find

Union-find in VHDL

giant

GIAnT, the Generic Implementation ANalysis Toolkit

gng

Growing neural gas in Racket

higher-order-masked-aes-128

Higher-order Masking of AES-128 based on the Rivain and Prouff method, CPRR method and Common Shares with Random Reduction method.

jazzer

Coverage-guided, in-process fuzzing for the JVM

jazzer.js

Coverage-guided, in-process fuzzing for Node.js

my-first-r-d-project

Utility-based agent in a grid world.

oetr.github.io

racket-hdf5

FFI bindings to the hdf5 library

racket-opencv

FFI bindings for OpenCV in Racket

racket-plplot

FFI bindings to PLplot

racket-processor

Racket VM on FPGAs

simsim

ATMega163 Simulator

utterances

:crystal_ball: A lightweight comments widget built on GitHub issues